Asynchronous Digital Circuit Design (Workshops in Computing) by Graham Birtwistle, Alan Davis

By Graham Birtwistle, Alan Davis

Because the expenses of strength and timing develop into more and more tough to control in conventional synchronous structures, designers are being compelled to examine asynchronous possible choices. in response to transformed and multiplied papers from the VII Banff greater Order Workshop, this quantity examines asynchronous equipment that have been utilized in huge circuit layout, starting from preliminary formal specification to extra commonplace finite country computing device established keep watch over types. Written by means of best practitioners within the zone, the papers hide many elements of present perform together with useful layout, silicon compilation, and purposes of formal specification. it is also a cutting-edge survey of asynchronous layout. The ensuing quantity can be necessary to an individual drawn to designing right asynchronous circuits which express excessive functionality or low energy operation.

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E. Muller and W. S. Bartky. A theory of asynchronous circuits II. Digital Computer Laboratory 78, University of Illinois, March 1957. [94] C. Myers and T. Meng. Synthesis of timed asynchronous circuits. In Proceedings of the IEEE International Conference on Computer Design, pages 279-284. IEEE Computer Society Press, October 1992. [95] T. Nanya, Y. Ueno, H. Kagotani, M. Kuwako, and A. Takamura. TITAC: design of a quasi-delay-insensitive microprocessor. IEEE Design and Test, 11(2):50-63, Summer 1994.

Synthesis of asynchronous sequential circuits with multiple-input changes. IEEE Transactions on Computers, C-17(6):559-566, June 1968. [51] S. B. Furber, P. Day, J. D. Garside, N. C. Paver, and J. V. Woods. A micropipelined ARM. 10, September 1993. B. Furber, P. D. C. Paver, S. V. Woods. The design and evaluation of an asynchronous microprocessor. In Proceedings of the IEEE International Conference on Computer Design, pages 217-220. IEEE Computer Society Press, October 1994. [53] R. Ginosar and N.

The architecture is based on a novel looped micropipeline, which synchronizes instruction and data flowing in opposite directions. The processor makes careful use of arbiters to regulate the synchronization. Brunvand developed the NSR RISC microprocessor [17] at the University of Utah, using transition-signaling for control, bundled data, and a micropipelined datapath. Other micropipelined-based RISC designs have been proposed by David et al. [34] and Ginosar and Michell [53]. A delay-insensitive microprocessor, TITAC, has been developed by Nanya et al.

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